Introduction to VLSI Design
Typical Design Flow
High Level Design
Low Level Design
VLSI Design Challenge
• Increasing productivity yield
• Shorter design cycle with more product feature
• Reduce NRE (Non-Recursive Engineering Cost)
• Design reuse enable
• Increase flexibility to design changes
• Faster exploitation of alternative architecture
• Faster exploitation of alternative libraries
• Better & Easier design auditing & verification
Click Here
Typical Design Flow
High Level Design
Low Level Design
VLSI Design Challenge
• Increasing productivity yield
• Shorter design cycle with more product feature
• Reduce NRE (Non-Recursive Engineering Cost)
• Design reuse enable
• Increase flexibility to design changes
• Faster exploitation of alternative architecture
• Faster exploitation of alternative libraries
• Better & Easier design auditing & verification
Click Here
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